View IDT709149S_342517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM
Features
x x
IDT709149S
x
x x
Architecture based on Dual-Port SRAM cells Allows full simultaneous access from both ports High-speed clock-to-data output times Commercial: 8/10/12ns (max.) Low-power operation IDT709149S Active: 1500mW (typ.) Standby: 75mW (typ.) 4K X 9 bits Synchronous operation 4ns setup to clock, 1ns hold on all control, data, and address inputs Data input, address, and control registers Fast 8ns clock to data out
x
x x x x
13ns cycle time, 76MHz operation in pipeline mode Self-timed write allows for fast cycle times TTL-compatible, singles 5V (10%) power supply Clock Enable feature Guaranteed data output hold times Industrial temperature range (40C to +85C) is available for selected speeds.
Description
The IDT709149 is a high-speed 4K x 9 bit synchronous Dual-Port SRAM. The memory array is based on Dual-Port memory cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up and hold times. The timing latitude provided by this approach will allow systems to be designed with very
Functional Block Diagram
REGISTER
REGISTER
I/O0-8L
WRITE LOGIC SENSE AMPS
MEMOR MEMORY Y ARRAY ARRAY DECODER DECODER
WRITE LOGIC SENSE AMPS
I/O0-8R FT/PIPEDR
0/1 0 1
OEL CLKL CLKENL Selftimed Write Logic
REG en
REG en
OER CLKR CLKENR Selftimed Write Logic
R/WL CEL
REG
REG
R/WR CER
3494 drw 01
A0L-A11L A0R-A11R
SEPTEMBER 1999
1
(c)1999 Integrated Device Technology, Inc. DSC-3494/4
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
short cycle times. This device has been optimized for applications having unidirectional data flow or bi-directional data flow in bursts, by utilizing input data registers. The IDT709149 utilizes a 9-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/reception error checking.
Fabricated using IDTs CMOS high-performance technology, these Dual-Ports typically operate on only 800mW of power at maximum high-speed clock-to-data output times as fast as 8ns. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT709149 is packaged in an 80-pin TQFP.
Reference
N/C A6L A7L A8L A9L A10L A11L N/C OEL VCC VCC R/WL N/C N/C CEL GND I/O8L I/O7L I/O6L N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
N/C N/C A5L A4L A3L A2L A1L A0L CLKENL CLKL CLKR CLKENR A0R A1R A2R A3R A4R A5R A6R N/C
IDT709149PF PN80-1(4) 80-Pin TQFP Top View(5) N/C A7R A8R A9R A10R A11R N/C , OER FT/PIPEDR GND GND R/WR N/C N/C CER GND I/O8R I/O7R I/O6R N/C
3494 drw 02
Pin Configurations(1,2,3)
NOTES: 1. All VCC pins must be connected to power supply. 2. All ground pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4, This package code is used to reference the package diagram. 5. This text does not indicate the orientaion of the actual part-marking.
N/C N/C I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L GND GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R N/C N/C
6.42 2
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Terminal Voltage Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Unit V
Maximum Operating Temperature and Supply Voltage(1,2)
Grade Commercial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10%
3494 tbl 02
VTERM(2) TBIAS TSTG IOUT
-0.5 to VCC -55 to +125 -55 to +125 50
V
o
Industrial
C C
o
NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
mA
3494 tbl 01
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0
____ ____
Max. 5.5 0 6.0
(2)
Unit V V V V
3494 tbl 03
0.8
Capacitance (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 8 9 Unit pF pF
3494 tbl 04
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V 10%)
709149S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to VCC VOUT = 0V to VCC IOL = +4mA IOH = -4mA Min.
___ ___ ___
Max. 10 10 0.4
___
Unit A A V V
3494 tbl 05
2.4
NOTE: 1. At VCC < 2.0V, input leakages are undefined
6.42 3
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4,5) (VCC = 5V 10%)
709149S8 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition CEL and CER = VIL, Outputs Open f = fMAX(1) CEL and CER = VIH f = fMAX(1) CE"A" = VIL and CE"B" = VIH(3) Active Port Outputs Open, f=fMAX(1) CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VCC - 0.2V(3) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open, f = fMAX(1) Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND Typ.
____ ____ ____ ____ ____ ____
709149S10 Com'l Only Typ.
____ ____ ____ ____ ____ ____
709149S12 Com'l Only Typ.
____ ____ ____ ____ ____ ____
Max. 320
____
Max. 310
____
Max. 300
____
Unit mA
ISB1
150
____
150
____
140
____
mA
ISB2
230
____
220
____
210
____
mA
ISB3
____
15
____
____
15
____
____
15
____
mA
____
____
____
ISB4
____ ____
220
____
____ ____
210
____
____ ____
200
____
mA
NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25C for Typ, and are not production tested. ICC DC = 150mA (Typ). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3494 tbl 0 6
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3
3494 tbl 07
8 7 6
9pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance
5V 893 DATAOUT 347 30pF DATAOUT 347
5V 893
tCD (Typical, ns)
5 4 3 2
5pF*
1 0
,
3494 drw 03
3494 drw 04
-1
20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
3494 drw 05
,
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42 4
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(4)
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
709149S8 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tCD1 tCD2 tS tH tDC tCKLZ tCKHZ tOE tOLZ tOHZ tSCK tHCK tCWDD Parameter Clock Cycle Time (Flow-Through) (3) Clock Cycle Time (Pipelined)
(3) (3)
709149S10 Com'l Only Min. 20 15 7 7 6 6
____ ____
709124S12 Com'l Only Min. 20 16 8 8 6 6
____ ____
Min. 16 13 6 6 6 6
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3494 tbl 08
Clock High Time (Flow-Through) Clock Low Time (Flow-Through) Clock High Time (Pipelined) (3) Clock Low Time (Pipelined)
(3)
(3)
Clock to Data Valid (Flow-Through) Clock to Data Valid (Pipelined) Registered Signal Set-up Time Registered Signal Hold Time Data Output Hold After Clock High Clock High to Output Low-Z
(1,2) (1,2) (3)
(3)
____ ____
12 8
____ ____ ____ ____
15 10
____ ____ ____ ____
20 12
____ ____ ____ ____
4 1 1 2
____ ____
4 1 1 2
____ ____
5 1 1 2
____ ____
Clock High to Output High-Z
7 8
____
7 8
____
9 10
____
Output Enable to Output Valid Output Enable to Output Low-Z
(1,2) (1,2)
0
____
0
____
0
____
Output Disable to Output High-Z
7
____ ____
7
____ ____
9
____ ____
Clock Enable, Disable Set-Up Time Clock Enable, Disable Hold Time Write Port Clock High to Read Data Delay
4 1
____
4 1
____
5 1
____
25
30
35
NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The Pipelined output parameters (tCYC2, tCD2) always apply to the Left Port. The Right Port uses the Pipelined tCYC2 and tCD2 when FT/PIPEDR = VIH and the FlowThrough parameters (tCYC1, tCD1) when FT/PIPEDR = VIL. 4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42 5
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output on Right Port (FT/PipedR = VIL)
tCYC1 CLK tCH1 tCL1 tSCK CLKEN tS CE tH tHCK tSCK
R/W
ADDRESS
An tCD1
An + 1 tDC Qn tCKLZ (1)
An + 2
An + 3 tCKHZ (1)
DATAOUT
Qn + 1 tOHZ
(1)
Qn + 1 tOLZ tOE
3494 drw 06 (1)
OE
Timing Waveform of Left Port Write to Flow-Through Right Port Read (FT/PipedR = VIL)(2,3)
CLK "L"
R/W "L"
ADDR "L"
MATCH
NO MATCH
DATA IN "L"
VALID
VALID
tCCS CLK "R"
R/W "R"
ADDR "R"
MATCH
NO MATCH
tCWDD DATA OUT "R"
VALID
tCD1
VALID
tDC
3494 drw 07
NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CEL = CER = VIL, CLKENL = CLKENR = VIL 3. OE = VIL for the reading port, port 'R'.
6.42 6
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation (Left Port; Right Port when FT/PipedR = VIH)(3)
tCYC2 tCH2 CLK CE tS tH tS tH tCL2
R/W tS An (1 Latency) DATAOUT tCKLZ OE
(2) (1)
tH
ADDRESS
An + 1 tCD2
An + 2 tDC Qn Qn + 1
An + 3 tCD2 Qn + 2
(1)
tOHZ
tOLZ
(1)
tOE
3494 drw 08
NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. CLKENL and CLKENR = VIL.
6.42 7
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)
tCYC2 tCH2 tCL2 CLK
CE tS tH tS R/W tS tH tH
ADDRESS
An tS tH
An +1
An + 2
An + 2 tS tH
An + 3
An + 4
DATAIN
(2)
Dn + 2 tCD2 Qn READ NOP
(3)
tCKHZ
(1)
tCKLZ
(1)
tCD2 Qn + 3
DATAOUT
WRITE
READ
3494 drw 09
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)
tCH2 CLK tS CE tS R/W tS tH An + 4 tH tH tCYC2 tCL2
ADDRESS tS DATAIN
An tH
An +1
An + 2 tS tH
An + 3
An + 5
(2)
tCD2 Qn tOHZ
(1)
Dn + 2
Dn + 3
tCKLZ(1)
tCD2 Qn + 4
DATAOUT
OE READ WRITE READ
3494 drw 10
NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 8
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
The IDT709149 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is dependent only on the low to high transitions of the clock signal to initiate a write allowing the shortest
possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. When piplelined mode is enabled, two cycles are required with CE LOW to reactivate the outputs.
Truth Table I: Read/Write Control(1)
Inputs Synchronous(3) CLK CE H L L X R/W X L H X Asynchronous OE X X L H I/O0-8 High-Z DATAIN DATAOUT High-Z DeselectedPower Down Selected and Write Enable Read Selected and Data Output Enabled Read (1 Latency) Data I/O Disabled
3494 tbl 09
Outputs Mode
Truth Table II: Clock Enable Function Table(1)
Inputs Operating Mode Load "1" Load "0" Hold (do nothing) CLK(3) X CLKEN(2) L L H H Register Inputs ADDR H L X X DATAIN H L X X Register Outputs(4) ADDR H L NC NC DATAOUT H L NC NC
3494 tbl 10
NOTES: 1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change 2. CLKEN = VIL must be clocked in during Power-Up. 3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOWto-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK. 4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.
6.42 9
IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range
Blank
Commercial (0C to +70C)
PF
80-pin TQFP (PN80-1)
8 10 12 S 709149
Commercial Only Commercial Only Commercial Only Standard Power
Speed in nanoseconds
36K (4K x 9-Bit) Synchronous Pipelined Dual-Port RAM
3494 drw 11
NOTE: 1. Industrial temperature range is available. For specific speeds, packages and poewrs contact your sales office.
Datasheet Document History
3/8/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Changed drawing format Removed Preliminary
6/3/99: 9/1/99:
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
6.42 10
for Tech Support: 831-754-4613 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

▲Up To Search▲

Price & Availability of IDT709149S

	To Download IDT709149S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .